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Cache simulator and visualizer
Coded from scratch, this was submitted as my final project for ECS 201. It simulated DLX assembly code and showed the state of the entire system as the program was run. It was mainly created to show how different cache setups would affect how long a program would take to complete, and how well a cache component was being utilized. Any number of caches could be simulated at once, all with different components and component settings. Several recently developed cache components were included. This is different from most other cache simulators, which only allow testing of standard associative, direct mapped, or prefetch buffer components.